Conventional personal computers and an increasing number of consumer electronic devices rely on a similar base hardware platform to perform signal processing. Typically, this base hardware platform includes a central processing unit (“CPU”), main system memory, input/output (“I/O”) devices, and storage devices. Several interconnect channels, providing connectivity between the functional components, enable data, commands, and control signals to flow between each component. Main system memory provides the CPU access to its contents, which include data and programs, using a variety of standards-based I/O interconnect channels, or bus interfaces. Typically, the type of memory determines which standards-based I/O bus interface connects the CPU to the main system memory.
The I/O bus interface between the main system memory and the CPU defines the data transmission rules, or protocol, and the electrical signaling requirements of the communication channel between the two devices. Often, a controller manages the complex processing of commands, data, and signaling between the CPU and the main system memory. A controller can be implemented in a variety of ways, such as a stand-alone semiconductor device or a functional block, residing within the CPU, co-processor, or digital signal processor (“DSP”). A computer system with a CPU connected to main system memory, using an I/O bus, is one example of a host system.
System architects commonly use various types of synchronous random access memory (“SDRAM”) as the main system memory. Single data rate (“SDR”) SDRAM, one example of SDRAM, operates by sending and receiving data and commands to and from the controller only during the rising edge of a clock common to CPU and the SDR SDRAM device. Sending and receiving data once during a clock cycle is recognized by those skilled in the art as single data rate transmission.
DDR SDRAMs, on the other hand, support data transfers on both the rising and falling edges of a clock signal in a given clock cycle, theoretically doubling the memory chip's data throughput. DDR SDRAMs transmit data (“DQ”) during both the rising and falling edges of a data strobe (or “DQS”), distinguished from transmitting data using only the rising edge of the system clock in SDR SDRAM applications. The data strobe is commonly a nonfree-running signal, generated by the device driving the data bus (the controller for write operations, the DRAM for read operations). In both read and write operations, the data strobe is derived from a clock provided by the memory controller. Using a separate data strobe enables DDR SDRAMs to operate at higher bandwidths compared to SDR SDRAMs.
Applications requiring high performance data processing often use DDR SDRAM as main system memory because of its performance, reliability, and cost savings. Nevertheless, as the performance of DDR SDRAM increased, the complexities associated with achieving the required timing relationship between controller and the DDR SDRAM have become increasingly difficult. The timing relationship between the controller and the DDR SDRAM depends on the uncertainty of the placement of the data relative to DQS during read and write operations.
The DDR SDRAM bus interface standard defines the timing relationship between data and DQS differently for read and write operations. For read operations, the DDR SDRAM presents the data and DQS signals to the controller edge aligned. Accordingly, the rising edge of the data occurs at relatively the same time as the rising edge of DQS at the input pins of the controller. The controller then delays the DQS relative to the data, aligning the rising edge of DQS with the center of the data signal to enable proper sampling. For a write cycle, the DDR SDRAM requires the DQS strobe to be centered with each data signal entering the memory device. Using this approach, the delay circuitry resides only in the controller and does not have to be reproduced in each DRAM device in a system.
Typically, a DDR SDRAM interface contains multiple data signals, operating as a parallel bus. Memory interface designers generally try to minimize the uncertainty of the placement of data relative to DQS by matching physical routing lengths of each data signal between the controller and the DDR SDRAM. As the width of a main system memory data bus increases, matching routing lengths becomes difficult and time consuming. Yet, any skew, jitter or uncertainty with regard to the placement of data in relation to DQS can reduce the memory throughput. Specifically during the write operation, significant skew results from the differences in routing length and other electrical parameters of the interface signal traces.
Skew may also result from the difference in phase between the clock domain associated with the DDR SDRAM and DQS. This type of skew causes sampling jitter, which also reduces the data valid window. The DDR SDRAM specifies the phase relationship between the clock associated the memory and the DQS generated from the controller. It will be appreciated by one of ordinary skill in the art that designers typically delay DQS relative to data on a write operation in order to comply with timing constrains of the DDR SDRAM. However, this approach increases the likelihood of violating the phase constraints between DQS domain and the clock domain. Therefore, there is a need for a system to support DDR SDRAM write operations using a controller that shifts the data relative to DQS while complying with the timing constraints between the DQS and clock domain.